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Verilog Arrays

Verilog arrays are used to group elements into multi-dimensional objects to be manipulated more easily. The Verilog does not have user-defined types, and we are restricted to arrays of built-in Verilog types such as nets, regs, and other Verilog variable types.

An array is a collection of the same types of variables and accessed using the same name plus one or more indices.

Each array dimension is declared by having the min and max indices within the square brackets. Array indices can be written in either direction:

A multi-dimensional array can be declared by having multiple dimensions after the array declaration.

Any square brackets before the array identifier are part of the data type replicated in the array.

Verilog arrays are synthesizable so that we can use them in a synthesizable RTL code.

In C, arrays are indexed from 0 by integers, or converted to pointers. But the whole array can be initialized, and each element must be read or separately written in procedural statements.

In Verilog-2001, arrays are indexed from left-bound to right-bound. If they are vectors, they can be assigned as single units, but not if they are arrays. Verilog-2001 allows for multiple dimensions.

In Verilog-2001, all data types can be declared as arrays. The wire, reg, and all other net types can also have a vector width declared. A dimension declared before the object name is referred to as the vector width dimension.

The Verilog-2005 specification also calls a one-dimensional array with elements of type reg a memory. It is beneficial for modeling memory elements such as read-only memory (ROM), and random access memory (RAM).

The dimensions declared after the object name is referred to as the array dimensions. Arrays hold a fixed number of equally-sized data elements.

Individual elements are accessed by index using a consecutive range of integers. Some arrays allow access to individual elements using non-consecutive values of any data types.

Arrays can be classified as fixed-sized arrays, also known as static arrays whose size cannot change once their declaration is made, or dynamic arrays can be resized.

Verilog had only one type of array. Verilog arrays can be either packed or unpacked. Packed array refers to dimensions declared after the type and before the data identifier name. Unpacked array refers to the dimensions declared after the data identifier name.

Packed or Fixed Arrays

In Verilog, the term packed array refers to the dimensions declared before the object name.

A one-dimensional packed array is also called a vector. Packed array divides a vector into subfields, which can be accessed as array elements. A packed array is guaranteed to be represented as a contiguous set of bits in simulation and synthesis.

Packed arrays can be made of only the single-bit data types bit, logic, reg, enumerated types, and other packed arrays and packed structures. This also means we cannot have packed arrays of integer types with predefined widths.

The maximum size of a packed array can be limited but shall be at least 65536 (216) bits.

A packed array is guaranteed to be represented as a contiguous set of bits.

Unpacked Arrays

In Verilog, the term unpacked array is used to refer to the dimensions declared after the object name.

Unpacked arrays can be made of any data type. Each fixed-size dimension is represented by an address range, such as [0:1023].

Or a single positive number to specify the size of a fixed-size unpacked array, such as [1024]. The notation size is equivalent to [0:size-1].

An unpacked array may or may not be so represented as a contiguous set of bits.

Multi-dimensional Arrays

Multi-dimensional arrays can be declared with both packed and unpacked dimensions. Creating a multi-dimensional packed array is analogous to slicing up a continuous vector into multiple dimensions.

When an array has multiple dimensions that can be logically grouped, it is useful to use the typedef to define the multi-dimensional array in stages to enhance readability.

Verilog Arrays Indexing and Slicing

Verilog arrays could only be accessed one element at a time. In Verilog arrays, we can also select one or more contiguous elements of an array. This is called a slice.

An array slice can only apply to one dimension; other dimensions must have single index values in an expression.

Verilog Array Operations

Verilog arrays support many more operations than their traditional Verilog counterparts.

  • +: and -: Notation

When accessing a range of a Verilog array slice, we can specify a variable slice by using the [start+: increment width] and [start-: decrement width] notations.

They are simpler than needing to calculate the exact start and end indices when selecting a variable slice. The increment or decrement width must be a constant.

  • Assignments and Copying Operations

Verilog arrays support many more operations. The following operations can be performed on both packed and unpacked arrays.

  • Packed Array Assignment

A Verilog packed array can be assigned at once, such as a multi-bit vector, an individual element or slice, and more.

  • Unpacked Array Assignment

All or multiple elements of a Verilog unpacked array can be assigned to a list of values.

The list can contain values for individual array elements, or a default value for the entire array.


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