Bidirectional Shift Register

Flip flops can be used to store a single bit of binary data (1or 0). However, to store multiple bits of data, we need multiple flip flops. N flip flops are to be connected to store n bits of data.

A Register is a device that is used to store such information. It is a group of flip flops connected in series used to store multiple bits of data.

The information stored within these registers can be transferred using shift registers.

A shift register is a cascade of flip-flops where one flop's output pin q is connected to the next data input pin (d). Because all flops work on the same clock, the bit array stored in the shift register will shift by one position.

For example, if a 5-bit right shift register has an initial value of 10110 and the input to the shift register is tied to 0, then the next pattern will be 01011 and the next 00101.

Bidirectional shift registers are the storage devices capable of shifting the data either right or left, depending on the mode selected.

The following image shows an n-bit bidirectional shift register with serial data loading and retrieval capacity. Initially, all the flip flops in the register are reset by driving their clear pins high.

R/L control line is made either low or high to opt for either left-shift or right-shift of the data bits, respectively.

An n-bit shift register can be formed by connecting n flip-flops where each flip flop stores a single bit of data.

The registers which will shift the bits to the left are called Shift left registers. The registers which will shift the bits to the right are called Shift right registers. Shift registers are basically of four types, such as:

Serial In Serial Out shift register
Serial In parallel Out shift register
Parallel In Serial Out shift register
Parallel In parallel Out shift register

Example

In this shift register example, we take five inputs and one n-bit output and the design is parameterized using parameter MSB to signify the width of the shift register.

If n is 4, then it becomes a 4-bit shift register. If n is 8, then it becomes an 8-bit shift register. This shift register has a few key features:

It can be enabled or disabled by driving en pin.
It can shift to the left as well as right when dir is driven.
If rstn is pulled low, it will reset the shift register, and output will become 0.
The input data value of the shift register can be controlled by d pin.

module shift_reg  #(parameter MSB=8) (  input d,               // Declare input for data to the first flop in the shift register
                                        input clk,                    // Declare input for the clock to all flops in the shift register 
                                        input en,                     // Declare input for enable to switch the shift register on/off
                                        input dir,                    // Declare input to shift in either left or right direction
                                        input rstn,                   // Declare input to reset the register to a default value
                                        output reg [MSB-1:0] out);    // Declare output to read out the current value of all flops in this register


   // This always block will "always" be triggered on the rising edge of the clock 
   // Once it enters the block, it will first check to see if reset is 0 and if yes, then reset register 
   // If no, then check to see if the shift register is enabled
   // If no => maintain previous output. If yes, then shift based on the requested direction

   always @ (posedge clk)
      if (!rstn)
         out <= 0;
      else begin
         if (en)
            case (dir)
               0 :  out <= {out[MSB-2:0], d};
               1 :  out <= {d, out[MSB-1:1]};
            endcase
         else
            out <= out;
      end
endmodule

Hardware Schematic

Testbench

The testbench is used to verify the functionality of this shift register. The example is instantiated into the top module, and the inputs are driven with different values. The behavior for each of the inputs can be observed at the output out pin.

module tb_sr;
   parameter MSB = 16;        // [Optional] Declare a parameter to represent number of bits in shift register

   reg data;                  // Declare a variable to drive d-input of design
   reg clk;                   // Declare a variable to drive clock to the design
   reg en;                    // Declare a variable to drive enable to the design
   reg dir;                   // Declare a variable to drive direction of shift register
   reg rstn;                  // Declare a variable to drive reset to the design
   wire [MSB-1:0] out;        // Declare a wire to capture output from the design

   // Instantiate design (16-bit shift register) by passing MSB and connect with TB signals
   shift_reg  #(MSB) sr0  (  .d (data),
                             .clk (clk),
                             .en (en),
                             .dir (dir),
                             .rstn (rstn),
                             .out (out));

   // Generate clock time period = 20ns, freq => 50MHz
   always #10 clk = ~clk;

   // Initialize variables to default values at time 0
   initial begin
      clk <= 0;
      en <= 0;
      dir <= 0;
      rstn <= 0;
      data <= 'h1;
   end

   // Drive main stimulus to the design to verify if this works
   initial begin

      // 1. Apply reset and deassert reset after some time
      rstn <= 0;
      #20 rstn <= 1;
          en <= 1;

	  // 2. For 7 clocks, drive alternate values to data pin
      repeat (7) @ (posedge clk)
         data <= ~data;

     // 3. Shift direction and drive alternate value to data pin for another 7 clocks
      #10 dir <= 1;
      repeat (7) @ (posedge clk)
         data <= ~data;

      // 4. Drive nothing for the next 7 clocks, allow shift register to shift based on dir simply
      repeat (7) @ (posedge clk);

      // 5. Finish the simulation
      $finish;
   end

   // Monitor values of these variables and print them into the log file for debug
   Initial
      $monitor ("rstn=%0b data=%b, en=%0b, dir=%0b, out=%b", rstn, data, en, dir, out);
endmodule

Serial-In Serial-Out Shift Register (SISO)

The shift register, which allows serial input (one bit after the other through a single data line) and produces a serial output, is known as the Serial-In Serial-Out shift register.

Since there is only one output, the data leaves the shift register one bit simultaneously in a serial pattern, thus the name Serial-In Serial-Out Shift Register.

The logic circuit given below shows a serial-in serial-out shift register. The circuit consists of four D flip-flops which are connected serially.

All these flip-flops are synchronous since the same clock signal is applied on each flip flop.

The above circuit is an example of a shift right register, taking the serial data input from the flip flop's left side. The main use of a SISO is to act as a delay element.

Serial-In Parallel-Out shift Register (SIPO)

The shift register, which allows serial input (one bit after the other through a single data line) and produces a parallel output, is known as the Serial-In Parallel-Out shift register.

The logic circuit given below shows a serial-in-parallel-out shift register. The circuit consists of four D flip-flops which are connected.

The clear (CLR) signal is connected, and the clock signal to all the 4 flip flops to RESET them. The first flip flop's output is connected to the next flip flop's input and so on.

All these flip-flops are synchronous since the same clock signal is applied on each flip flop.

The above circuit is an example of a shift right register, taking the serial data input from the flip flop's left side and producing a parallel output.

They are used in communication lines where a data line's demultiplexing into several parallel lines is required because the main use of the SIPO register is to convert serial data into parallel data.

Parallel-In Serial-Out Shift Register (PISO)

The shift register, which allows parallel input (data is given separately to each flip flop and simultaneously) and produces a serial output, is known as the Parallel-In Serial-Out shift register.

The logic circuit given below shows a parallel-in-serial-out shift register. The circuit consists of four D flip-flops which are connected.

The clock input is directly connected to all the flip flops. The input data is still connected individually to each flip flop through a multiplexer at every flip flop's input.

The output of the previous flip flop and parallel data input is connected to the MUX input, and the output of MUX is connected to the next flip flop.

All these flip-flops are synchronous since the same clock signal is applied to each flip flop.

A Parallel in Serial out (PISO) shift registers used to convert parallel data to serial data.

Parallel-In Parallel-Out Shift Register (PIPO)

The shift register allows parallel input (data is given separately to each flip flop and simultaneously) and produces a parallel output, known as the Parallel-In parallel-Out shift register.

The logic circuit given below shows a parallel-in-parallel-out shift register. The circuit consists of four D flip-flops which are connected. The clear (CLR) signal and clock signals are connected to all the 4 flip flops.

There are no interconnections between the individual flip-flops in this type of register since no serial shifting of the data is required.

Data is given as input separately for each flip flop and in the same way, and output is also collected individually from each flip flop.

A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device, and like the SISO Shift register, it acts as a delay element.

Bidirectional Shift Register

If we shift a binary number to the left by one position, it is equivalent to multiplying the number by 2. If we shift a binary number to the right by one position, it is equivalent to dividing the number by 2.To perform these operations; we need a register that can shift the data in either direction.

Bidirectional shift registers are the registers capable of shifting the data either right or left, depending on the mode selected.

If the mode selected is 1(high), then the data will be shifted towards the right direction, and if the mode selected is 0(low), then the data will be shifted towards the left direction.

The logic circuit given below shows a Bidirectional shift register. The circuit consists of four D flip-flops which are connected.

The input data is connected at two ends of the circuit, and depending on the mode selected, only one and gate are in the active state.

Applications of shift Registers

Here are the following applications of the shift registers, such as:

The shift registers are used for temporary data storage.
The shift registers are also used for data transfer and data manipulation.
The serial-in serial-out and parallel-in parallel-out shift registers are used to produce time delay to digital circuits.
The serial-in parallel-out shift register is used to convert serial data into parallel data. They are used in communication lines where demultiplexing of a data line into several parallel lines is required.
A Parallel in Serial out shift register is used to convert parallel data to serial data.

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