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Verilog Case Statement

The case statement checks if the given expression matches one among the other expressions inside the list and branches. It's typically accustomed implement a device.

The if-else construct may not be applicable if there unit of measurement many conditions to be checked and would synthesize into a priority encoder instead of a device.

In Verilog, a case statement includes all of the code between the Verilog keywords, case ("casez", "casex"), and endcase. A case statement can be a select-one-of-many construct that is roughly like Associate in nursing if-else-if statement.

Syntax

A Verilog case statement starts with the case keyword and ends with the endcase keyword.

The expression within parentheses area unit aiming to be evaluated specifically once and is compared with the list of alternatives inside the order they are written.

And the statements that the selection matches the given expression unit of measurement dead. A block of multiple statements ought to be sorted and be within begin and end.

If none of the case things match the given expression, statements within the default item unit of measurement dead. The default statement is non mandatory, and there's only one default statement throughout a case statement. Case statements are nested.

Execution will exit the case block whereas not doing one thing if none of the items match the expression, and a default statement is not given.

Example

The following vogue module includes a 2-bit opt for signal to route one among the three different 3-bit inputs to the sign stated as out.

A case statement is used to assign the correct input to output supported the value of sel. Since sel can be a 2-bit signal, it'll have twenty 2 combos, zero through 3. The default statement helps to line output to zero if sel is 3.

Case Statement Header

A case statement header consists of the case ("casez", "casex") keyword followed by the case expression, usually all on one line of code.

When adding full_case or parallel_case directives to a case statement, the directives unit of measurement added as a comment in real time following the case expression at the tip of the case statement header and before any of the case things on ensuing code lines.

Case item

The case item is that the bit, vector, or Verilog expression accustomed compare against the case expression.

Unlike different high-level programming languages like 'C', the Verilog case statement includes implicit break statements.

The first case item that matches this case expression causes the corresponding case item statement to be dead, thus all of the rest of the case things unit of measurement skipped for this undergo the case statement.

Case item statement

A case item statement is one or plenty of Verilog statements dead if the case item matches this case expression. Not like VHDL, Verilog case things can themselves be expressions.

To alter the parsing of Verilog code document, Verilog case item statements ought to be enclosed between the keywords "begin" and "end" if over one statement is to be dead for a specific case item.

Casez

In Verilog, there is a casez statement, a variation of the case statement that enables "z" and "?" values to be treated throughout case-comparison as "don't care" values.

"Z" and "?" unit of measurement treated as a don't care if they are inside the case expression or if they are inside the case item.

When secret writing a case statement with "don't care," use a casez statement and use "?" characters instead of "z" characters inside the case things to purpose "don't care" bits.

Casex

In Verilog, there is a casex statement, a variation of the case statement that enables "z", "?", and "x" values to be treated throughout comparison as "don't care" values.

"x", "z" and "?" unit of measurement treated as a don't care if they are inside the case expression or if they are inside the case item.

Full Case Statement

A full case statement can be a case statement inside that all getable case-expression binary patterns are matched to a case item or a case default.

If a case statement does not embrace a case default, and it's getable to go looking out a binary case expression that does not match any of the printed case things, the case statement is not full.

A full case statement can be a case statement inside that every getable binary, non-binary, and mixture of binary and non-binary patterns is boxed in as a case item inside the case statement.

Verilog does not would like case statements to be either synthesis or high-density lipoprotein simulation full, but Verilog case statements is made full by adding a case default. VHDL desires case statements to be high-density lipoprotein simulation full, that usually desires Associate in Nursing "others" clause.

Parallel Case Statement

A parallel case statement can be a case statement inside that it's only getable to match a case expression to only one case item.

If it's getable to go looking out a case expression which may match over one case item, the matching case things unit of measurement stated as overlapping case things, and so the case statement is not parallel.

Hardware Schematic

The RTL code is elaborated to get a hardware schematic that represents a 4 to 1 multiplexer.

Verilog Case Statement

After executes the above design, the output is zero when sel is 3 and corresponds to the assigned inputs for other values.

In a case statement, the comparison only succeeds when each bit of the expression matches one of the alternatives including 0, 1, x and z. In the above example, if any of the bits in sel is either x or z, the default statement will be executed because none of the other alternatives matched. In such a case, output will be all zeros.

If the case statement in design has x and z in the case item alternatives, the results will differ.

Differentiation between the case and if-else

The case statement is different from if-else-if in two ways, such as:

  • Expressions given in an if-else block are more general, while in a case block, a single expression is matched with multiple items.
  • The case will provide a definitive result when there are X and Z values in an expression.

Next TopicVerilog Parameters




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