Verilog Display Tasks
Display system tasks are mainly used to display informational and debug messages to track the simulation flow from log files. There are different groups of display tasks and formats in which they can print values.
Generally, display system tasks are grouped into three categories, such as:
When one of these tasks is invoked, it simply prints its arguments. The order of printed arguments is the same as the order that the x appears in the argument list. If no argument is specified, it can be declared a null argument, and when the display task is invoked, it simply prints a single space character. An argument can be an expression that returns a value and a quoted string.
Display and Write Tasks
The first group of displaying tasks is very similar to print the function in the ANSI C language. The $write and the $display tasks work in the same way, and the only difference is that the $display task adds a new line character at the end of the output, while the $write task does not.
Both $display and $write display arguments in the order they appear in the argument list.
$write does not append the newline character to the end of its string, while $display can be seen from the example shown below.
Now, executes the above code, and we will get the following output.
ncsim> run This ends with a new line This does not, like this. To start a new line, use newline char Hello! ncsim: *W,RNQUIE: Simulation is complete.
$strobe prints the final values of variables at the end of the current delta time-step and has a similar format like $display. A newline is automatically added to the text.
NOTE: $strobe shows the final updated value of the variable b at time 10ns, 0x2E, and $display picks that up only in the next simulation delta at 11ns.
And the output looks like:
ncsim> run [$display] time=10 a=0x2d b=0x2d [$strobe] time=10 a=0x2d b=0x2e [$display] time=11 a=0x2d b=0x2e [$strobe] time=11 a=0x2d b=0x2e ncsim: *W,RNQUIE: Simulation is complete. ncsim> exit
Verilog Continuous Monitors
$monitor helps to automatically print out variable or expression values whenever the variable or expression in its argument list changes.
It achieves a similar effect of calling $display after every time any of its arguments get updated. A newline is automatically added to the text.
$monitor is like a task that is spawned to run in the background of the main thread, which monitors and displays value changes of its argument variables. A new $monitor task can be issued any number of times during the simulation.
Verilog Format Specifiers
To print variables inside display functions, appropriate format specifiers have to be given for each variable.
These tasks have a special character (%) to indicate that the information about signal value is needed. When using a string, the compiler recognizes the % character and knows that the next character is a format specification.
If the format specification sign is used, a corresponding argument should always be followed (exception is the %m argument).
These system tasks can be invoked with "o", "h" and "b" extensions. For example $writeb, $writeo, and $displayh. When invoked, they inform the simulator that there are some arguments without corresponding format specifications, and the default display format should be changed. By default, $display and $write system tasks use the decimal format to change display formats.
The size of the displayed data is essential. Generally, it depends on the format specification. If we are using a hexadecimal format, the data will be displayed as four characters, each of them representing four bits of the value (a single hexadecimal value can be represented as four bits).
Similarly, octal values will be displayed as a group of characters representing three bits. The result of an expression is automatically sized. However, we can change default settings by adding 0 (zero) after the % character.
Another very useful display task feature is ruled applying to the result of an expression that has an unknown or high impedance value. If we are using the decimal format (%d), then we follow the following rules:
And if we are using hexadecimal (%h) and octal (%o) formats, we follow the following rules:
NOTE: In the octal format, a group represents three bits that can be represented as one digit within the range is 0 to 7. In the hexadecimal format, four bits can be represented as one character within the range 0 to 9 and characters in range a to f.
Above code gives the following output after the execution, such as:
ncsim> run a = 0e a = 14 a = 00001110 str = Hello time = 200 float_pt = 3.142000 float_pt = 3.142000e+00 ncsim: *W,RNQUIE: Simulation is complete.
Verilog Escape Sequences
Some characters are considered unique since they stand for other display purposes such as new-line, tabs, and form feeds.
To print these special characters, each occurrence of such characters has to be escaped.
And the output looks like:
ncsim> run Newline character Tab character stop Escaping " % ncsim: *W,RNQUIE: Simulation is complete.