JK Flip Flop

The JK flip-flop is the most versatile of the basic flip flops. A JK flip-flop is used in clocked sequential logic circuits to store one bit of data.

It is almost identical in function to an SR flip flop. The only difference is eliminating the undefined state where both S and R are 1. Due to this additional clocked input, a JK flip-flop has four possible input combinations, such as "logic 1", "logic 0", "no change" and "toggle".

Hardware Schematic

Example

We will program JK Flip Flop in Verilog and write a testbench for the same code.

module jk_ff ( input j, input k, input clk, output q);

   reg q;

   always @ (posedge clk)
      case ({j,k})
         2'b00 :  q <= q;
         2'b01 :  q <= 0;
         2'b10 :  q <= 1;
         2'b11 :  q <= ~q;
      endcase
endmodule

Testbench

module tb_jk;
   reg j;
   reg k;
   reg clk;

   always #5 clk = ~clk;

   jk_ff    jk0 ( .j(j),
                  .k(k),
                  .clk(clk),
                  .q(q));

   initial begin
      j <= 0;
      k <= 0;

      #5 j <= 0;
         k <= 1;
      #20 j <= 1;
          k <= 0;
      #20 j <= 1;
          k <= 1;
      #20 $finish;
   end

   initial
      $monitor ("j=%0d k=%0d q=%0d", j, k, q);
endmodule

Edge-triggered JK Flip-flop

The type of JK flip-flop described here is an edge-triggered JK flip-flop. It is built from two gated latches: one a master gated D latch and a slave gated SR latch.

This is a modified version of the edge-triggered D flip flop. The flip-flop's outputs are fed back and combined with the inputs. The master takes the flip-flop's inputs, such as J (set), K (reset), and C (clock).

The clock input is inverted and fed into the D latch's gate input. The slave takes the master's outputs as inputs (Q to S and Qn to R) and complements the master's clock input. The slave's outputs are the flip-flop's outputs. This difference in clock inputs between the two latches disconnects them and eliminates the transparency between the flip-flop's inputs and outputs.

The below schematic image shows a positive edge-triggered JK flip-flop. The two inputs J and K, are used to set and reset the data, respectively. They can also be used to toggle the data. The clock input C is used to control both the master and slave latches, making sure only one of the latches can set its data at any given time.

When C has the value 0, the master latch can set its data, and the slave latch cannot. When C has the value 1, the slave can set its data, and the master cannot. When C transitions from 0 to 1, the master has its outputs set, which reflect the flip-flop's inputs when the transition occurred.

The outputs Q and Qn are the flip-flop's stored data and the complement of the flip-flop's stored data.

The schematic symbol for a 7476 edge-triggered JK flip-flop is shown below. This chip has inputs to set and reset the flip-flop's data asynchronously.

Example

Below is the Verilog code for a positive edge-triggered JK flip-flop. An active-low reset input has been added to asynchronously clear the flip-flop.

module jk_ff_edge_triggered(Q, Qn, C, J, K, RESETn);
   output Q;
   output Qn;
   input  C;
   input  J;
   input  K;
   input  RESETn;

   wire   Kn;                      // The complement of the K input.
   wire   D;   
   wire   D1;                      // Data input to the D latch.   
   wire   Cn;                      // Control input to the D latch.
   wire   Cnn;                    // Control input to the SR latch.
   wire   DQ;                     // Output from the D latch, inputs to the gated SR latch (S).
   wire   DQn;                   // Output from the D latch, inputs to the gated SR latch (R).

   assign D1 = !RESETn ? 0 : D;                           // Upon reset force D1 = 0

   not(Kn, K);   
   and(J1, J, Qn);
   and(K1, Kn, Q);   
   or(D, J1, K1);   
   not(Cn, C);
   not(Cnn, Cn);   
   d_latch dl(DQ, DQn, Cn, D1);
   sr_latch_gated sr(Q, Qn, Cnn, DQ, DQn);   
endmodule                                      // jk_flip_flop_edge_triggered

module d_latch(Q, Qn, G, D);
   output Q;
   output Qn;
   input  G;   
   input  D;

   wire   Dn; 
   wire   D1;
   wire   Dn1;

   not(Dn, D);   
   and(D1, G, D);
   and(Dn1, G, Dn);   
   nor(Qn, D1, Q);
   nor(Q, Dn1, Qn);
endmodule                                     // d_latch

module sr_latch_gated(Q, Qn, G, S, R);
   output Q;
   output Qn;
   input  G;   
   input  S;
   input  R;

   wire   S1;
   wire   R1;
   
   and(S1, G, S);
   and(R1, G, R);   
   nor(Qn, S1, Q);
   nor(Q, R1, Qn);
endmodule                                    // sr_latch_gated

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