Lexical conventions in Verilog are similar to the C programming language. Verilog language source text files are a stream of lexical tokens.
A lexical token may consist of one or more characters, and every single character is in exactly one token.
The tokens can be keywords, comments, numbers, white space, or strings. All lines should be terminated by a semi-colon (;).
White space can contain the characters for tabs, blanks, newlines, and form feeds. These characters are ignored except when they serve to separate other tokens. However, blanks and tabs are significant in strings.
There are two types to represent the comments, such as:
We can specify constant numbers in binary, decimal, hexadecimal, or octal format. Negative numbers are represented in 2's complement form. The question mark (?) character is the Verilog alternative for the z character when used in a number. The underscore character (_) is legal anywhere in a number, but it is ignored as the first character.
1. Integer Number
Verilog HDL allows integer numbers to be specified as:
The syntax is given as:
2. Real Numbers
3. Signed and Unsigned Numbers
Verilog supports both the type of numbers, but with certain restrictions. In C language, we don't have int and unint types to say if a number is signed integer or unsigned integer.
Any number that does not have a negative sign prefix is positive. Or indirect way would be "Unsigned".
Negative numbers can be specified by putting a minus sign before the size for a constant number, thus become signed numbers. Verilog internally represents negative numbers in 2's complement format. An optional signed specifier can be added for signed arithmetic.
4. Negative Numbers
Negative numbers are specified by placing a minus (-) sign before the size of a number. It is illegal to have a minus sign between base_format and number.
The identifier is the name used to define the object, such as a function, module, or register. Identifiers should begin with alphabetical characters or underscore characters.
For example, A_Z and a_z.
Identifiers are a combination of alphabetic, numeric, underscore, and $ characters. They can be up to 1024 characters long.
1. Escaped Identifiers
Verilog HDL allows any character to be used in an identifier by escaping the identifier.
Escaped identifiers are including any of the printable ASCII characters in an identifier.
Operators are special characters used to put conditions or to operate the variables. There are one, two, and sometimes three characters used to perform operations on variables.
1. Arithmetic Operators
These operators perform arithmetic operations. The + and -are used as either unary (x) or binary (z-y) operators.
The operators included in arithmetic operation are addition, subtraction, multiplication, division, and modulus.
2. Relational Operators
These operators compare two operands and return the result in a single bit, 1 or 0. The Operators included in relational operation are:
3. Bit-wise Operators
Bit-wise operators do a bit-by-bit comparison between two operands. The Operators included in Bit-wise operation are:
4. Logical Operators
Logical operators are bit-wise operators and are used only for single-bit operands. They return a single bit value, 0 or 1. They can work on integers or groups of bits, expressions and treat all non-zero values as 1.
Logical operators are generally used in conditional statements since they work with expressions. The operators included in Logical operation are:
5. Reduction Operators
Reduction operators are the unary form of the bitwise operators and operate on all the bits of an operand vector. These also return a single-bit value. The operators included in Reduction operation are:
6. Shift Operators
Shift operators are shifting the first operand by the number of bits specified by the second operand in the syntax.
Vacant positions are filled with zeros for both directions, left and right shifts (There is no use sign extension). The Operators included in Shift operation are:
7. Concatenation Operator
The concatenation operator combines two or more operands to form a larger vector. The operator included in Concatenation operation is:
8. Replication Operator
The replication operator is making multiple copies of an item. The operator used in Replication operation is:
9. Conditional Operator
Conditional operator synthesizes to a multiplexer. It is the same kind as is used in C/C++ and evaluates one of the two expressions based on the condition. The operator used in Conditional operation is:
Operands are expressions or values on which an operator operates or works. All expressions have at least one operand.
Literals are constant-valued operands that are used in Verilog expressions. The two commonly used Verilog literals are:
2. Wires, Regs, and Parameters
Wires, regs, and parameters are the data types used as operands in Verilog expressions. Bit-Selection "x" and Part-Selection "x[4:2]"
Bit-selects and part-selects are used to select one bit and multiple bits, respectively, from a wire, regs or parameter vector using square brackets "[ ]".
3. Function Calls
In the Function calls, the return value of a function is used directly in an expression without first assigning it to a register or wire.
It just places the function call as one of the types of operands. It is useful to know the bit width of the return value of the function call.