Verilog Ring Counter
A ring counter is a digital circuit with a series of flip flops connected in a feedback manner. Ring Counter is composed of Shift Registers. The data pattern will re-circulate as long as clock pulses are applied.
The circuit is a special type of shift register where the last flip flop's output is fed back to the input of the first flip flop. When the circuit is reset, except one of the flip flop output, all others are made zero. For the n-flip flop ring counter, we have a MOD-n counter. That means the counter has n different states.
For example, if we take a 4-bit Ring Counter, then the data pattern will repeat every four clock pulses. If the pattern is 1000, it will generate 0100, 0010, 0001, 1000, etc.
Rotational Movement of a Ring Counter
Since the above example has four distinct states, it is also known as a modulo-4 or mod-4 counter, with each flip-flop output having a frequency value equal to one-fourth of the main clock frequency.
The MODULO or MODULUS of a counter is the number of states the counter counts or sequences through before repeating itself, and a ring counter can be made to output any modulo number.
A mod-n ring counter will require n number of flip-flops connected to circulate a single data bit providing n different output states.
In the above example, only four of the possible sixteen states are used, making ring counters very inefficient in their output state usage.