Switch Level Modeling
The switch level of modeling provides a level of abstraction between the logic and analog-transistor levels of abstraction. It describes the interconnection of transmission gates, which are abstractions of individual MOS and CMOS transistors.
The switch level transistors are modeled as being either on or off, conducting or not conducting. The values carried by the interconnections are abstracted from the whole range of analog voltages or currents to a small number of discrete values. These values are referred to as signal strengths.
Verilog also provides support for transistor level modeling. However, designers rarely use these days as the complexity of circuits has required them to move to higher levels of abstractions rather than use switch level modeling.
Usually, the transistor level modeling is referred to model in hardware structures using transistor models with analog input and output signal values.
On the other hand, gate-level modeling refers to modeling hardware structures wing gate models with digital input and output signal values between these two modeling schemes are referred to as switch level modeling.
The transistors only exhibit digital behavior and their input at the transistor level, and output signal values are only limited to digital values.
Verilog uses a 4 value logic value system, so Verilog switch input and output signals can take any of the four 0, 1, Z, and X logic values.
Switch Level Primitives
Switches are unidirectional or bidirectional and resistive or non-resistive for each group, those primitives that switch on with a positive gate such as NMOS transistor and those that switch on with a negative gate such as PMOS transistor.
Two types of MOS switches can be defined with the keywords nmos and pmos.
In Verilog, nmos and pmos switches are shown as the following:
Since switches are Verilog primitives such as logic gates, the name of the instance is optional. Therefore, it is acceptable to instantiate a switch without assigning an instance name.
The value of the out signal is determined from the values of data and control signals.
Some combinations of data and control signals cause the gates to output to either a 1 or 0 or a z value without a preference for either value. The symbol L stands for 0 or Z; H stands for 1 or z.
Thus, the nmos switch conducts when its control signal is 1. If the control signal is 0, the output assumes a high impedance value. Similarly, a pmos switch conducts if the control signal is 0.
CMOS switches are declared with the cmos keyword. A cmos device can be modeled with a nmos and a pmos device. A CMOS switch is instantiated as shown below, such as:
The ncontrol and pcontrol usually are complements of each other. When the ncontrol signal is 1, and the pcontrol signal is 0, the switch conducts. If ncontrol is 0 and pcontrol is 1, the output of the switch is high impedance value.
The cmos gate is essentially a combination of two gates: one nmos and one pmos. Thus the cmos instantiation shown above is equivalent to the following.
NMOS, PMOS and CMOS gates conduct from drain to source. It is important to have devices that conduct in both directions.
In such cases, signals on either side of the device can be the driver signal. Bidirectional switches are provided for this purpose.
Three keywords are used to define bidirectional switches, such as:
1. tran: The tran switch acts as a buffer between the two signals inout1 and inout2. Either inoutl or inout2 can be the driver signal.
2. tranif0: The tranif0 switch connects the two signals inout1 and inout2 only if the control signal is logical 0. If the control signal is a logical 1, then the nondriver signal gets a high impedance value z. The driver signal retains the value from its driver.
3. Tranif1: The tranif1 switch conducts if the control signal is a logical 1.
Resistive switches reduce signal strengths when signals pass through them. Regular switches retain strength levels of signals from input to output.