Field Effect Transistor

FET or Field Effect Transistor is also a type of transistor-like Bipolar Junction Transistor. FET is also known as JFET (Junction Field Effect Transistor).

Let's discuss the concept, structure, types with working, and characteristics of JFET in detail.

Structure

The Junction Field Effect Transistor has three terminals, drain, source, and gate. The structure and symbol of JFET are shown below:

Terminals of JFET

The three terminals of JFET are as follows:

Source

The source is the terminal at the bottom of the transistor, as shown above. The majority carriers' electrons (in the case of n-channel) and holes (in the p-channel) enter through the source into the transistor. The current generated due to the majority charge carriers through this terminal is known as source current (I_S).

Drain

A drain terminal is present at the top of the transistor. The majority carriers' electrons (in the case of n-channel) and holes (in the case of p-channel) exit from the transistor through the drain terminal. The current generated due to the majority charge carriers through this terminal is the drain current (I_D). The voltage is connected across the drain and source.

The direction of current in JFET is determined in the opposite direction to the flow of electrons and in the same direction to the flow of holes. The voltage between the drain and source is known as V_DS.

Gate

Gate consists of the heavily doped region present on both sides of the transistor. In the case of n-channel, two p-regions are present on the two sides of the transistor, named as the gate. The same procedure creates the impurities doped on the two regions as the p-n junctions.

The voltage between the gate and source is known as V_GS. It is applied in the direction to make the p-n junction reverse biased. The current generated through this terminal is known as gate current (I_G).

Channel

The part of the transistor where the n-type doping is present in large amounts is known as the channel. It is defined as the region between the two gate terminals that possess the movement of majority carriers from the source to the drain.

Voltages

There are two voltage sources V_DS and V_GS. Let's discuss the connection of these two voltage sources across the three terminals of the JFET.

V_DS

It is the voltage across the terminals D and S, i.e., drain and source. The connection of V_DS is such that its relation with the source describes the movement of charge carriers away from the S towards D. Its relation with drain describes the attraction of charge from the D to constitute the current.

It can be calculated as:

V_DS = V_D - V_S

V_GS

It is the voltage across the terminals G and S, i.e., gate and source. It is also known as the controlling voltage of JFET. It is intended to increase the drain current in the transistor.

Types of JFET

JFET is further categorized as n-channel JFET and p-channel JFET. The working of both the JFET are similar expect the majority carriers.

N-channel JFET

N-channel refers to the JFET with center channel doped with the N-type or Pentavalent impurities and the two side slabs doped with the P-type or trivalent impurities.

Construction

The structure of NPN JFET is shown below:

Here, D represents the Drain terminal, S represents the source, and G represents the gate terminal. V_DS and V_GS are the two voltage sources connected across the G, D, and S terminals. The connection is shown below:

The (+) terminal of the V_DS is connected to the drain and (-) terminal to the source. Similarly, the (+) terminal of the V_GS is connected to the source and (-) terminal to the gate.

Let's discuss its working.

Working

• When the voltage across the V_DS is switched ON, the electrons flow towards S. The gate voltage remains at zero volts. The electrons (majority carriers) of the n-channel start moving towards the D. It is because same charge repels each other.
• Some electrons deposits on the two p-type slabs at the corner, because opposite charge attracts. The depletion region is formed at the two slabs, as shown below:
  
• The electrons will flow towards the D through the space between the two depletion regions. It results in the current from the D to S.
• When the voltage across the V_GS is switched ON, the more charge is provided at the gate terminals that increase the depletion width of the two p -type layers. It is shown below:
  
• The flow of electrons from S decreases to the reduced gap between the depletion regions.
• The decrease in the voltage at V_DS and V_GS also reduces the width of the depletion region.
• The large negative bias will further increase the depletion width and the current starts decreasing due to the block of movement of electrons towards the drain. It is shown below:
  

P-channel JFET

P-channel refers to the JFET with center channel doped with the P-type impurities and the two side slabs doped with the N-type or Pentavalent impurities.

Construction

The structure of PNP JFET is shown below:

The working of the p-channel JFET is the same as that of the n-channel except for the majority charge carriers in both the Field-Effect Transistors. The charge carriers constituting the current flow in the p-channel are holes, and in the n-channel are electrons. The concept of the connection of the voltages across the three terminals is already discussed above.

The depletion width in the p-channel after applying the voltage across the G, D, and S terminals will appear as:

The (+) terminal of the V_DS is connected to the source and (-) terminal to the drain. Similarly, the (+) terminal of the V_GS is connected to the gate and (-) terminal to the source.

Note: The connection of both the JFET is opposite due to the difference of majority carriers' concentration in n-channel and p-channel.

JFET Formula

• The formula to calculate the drain current is given by:
  I_D = I_DSS (1 - V_GS/V_P)²
  Where,
  V_P is the pinch-off voltage
  I_DSS is the drain current only, but in the case of zero bias
  The drain can also be calculated using the formula given by:
  I_D = (V_DD - V_D) / R_D
  V_DD is also known as V_GS.
• The formula to calculate the R_GS (G - S resistance) is given by:
  R_GS = V_GS / I_G
• The transconductance of JFET is given by:
  G_m = ? I_D / ? V_GS
• The drain resistance (R_D) of JFET is given by:
  R_D = 1/ Gm = ? V_GS / ? I_D
• The amplification factor (u) of JFET is defined as the ratio of change in voltages of V_DS and V_GS. It is given by:
  U = ? V_DS / ? V_GS
• The pinch-off voltage can be calculated using the formula:
  V_P = V_GS - V_DS
  V_P = qN_Da²/2ε

We will discuss two examples based on the above formula later in the topic.

Pinch-off voltage

It is defined state of the transistor to turn OFF when the voltage falls below the threshold voltage V_T. It is also defined as the state of the transistor that removes all the free charge from the channel.

Characteristics

Here, we will discuss the characteristics of the n-channel JFET.

The characteristics with the D-S voltage on the X-axis with the drain current on the y-axis are shown below:

Consider the below JFET circuit.

Case 1:

In case of V_GS = 0 and I_D = 0, the S and G will not receive any voltage. It means that both terminals are open. But, when V_DS is applied across the D and S terminals, the transistor will start working with the help of a small applied voltage. The electrons will move from the S towards the drain constituting the small drain current. Thus, I_D will increase linearly with the applied V_DS.

At a point, the charge concentration will be high at the drain regions. It is a pinch-off condition, where D is more reverse biased than the S side. The current I_D will start approaching the constant value. The I_D responds more to V_GS and slightly to V_DS.

Case 2:

If V_GS is also applied across the terminals S and D, the pinch-off condition will occur at a rapid rate as compared to the first case. It is because both the V_GS and V_DS are applied to the transistor. The maximum ID will also be smaller.

The reverse bias voltages across the gate increase the drain voltage, increasing the effective voltage across the G junction.

The n-channel JFET requires the negative voltage at the S to allow electrons to move towards the D. The D junction requires the positive voltage to attract more electrons to constitute the current. The p-channel requires positive voltage at the S to allow holes to move towards the D. The D junction requires the negative voltage to attract more holes to constitute the current. We can use either end of the channel as the source or drain, and we only need to consider the polarities applied to both channels.

Mathematical model

We have already discussed that V_DS causes only a small change in the drain current of the transistor. But when V_GS is applied, the current increases. Let's consider the effective channel cross-section be A, which is constant.

Area of A = 2bw

Where,

2b is the channel width

W is the channel dimension perpendicular to the width

The drain current based on the Ohm's law can be written as:

I_D = AqN_Du_nε

Putting the value of A = 2bw, we get:

I_D = 2bwqN_Du_nε

Where,

N_D is the donor ions

We know ε = V_DS/ L

So,

I_D = 2bwqN_Du_nV_DS/ L

FET as a Voltage Variable Resistor

FET can work as a VVR in a specific region, and voltage Variable Resistor is also known as Voltage Dependent Resistor. The Field Effect transistor constitutes a small drain current when VDS is small, and it is the state before the pinch-off. The transistors work like a Voltage Variable Resistor in this region only, i.e., before the pinch-off. The resistance across the two junctions, D and S, is controlled by the voltage VGS. The VVR is used in various applications, such as audio amplifiers and television receivers.

FET vs. BJT

Let's discuss the differences between the Field Effect Transistor and Bipolar Junction Transistor.

Numerical Examples

Let's discuss two examples of JFET.

Example 1: A Junction Field Effect Transistor produces a gate current of 5nA. The gate is reverse biased at the voltage of 10 volts. Find the resistance between the drain and source terminal of the transistor?

Solution:

Given: V_GS = 10V and I_G = 5nA

We need to find the R_GS

We know, R_GS = V_GS / I_G

Putting the values in the given formula, we get:

R_GS = 10 / 5 x 10^-9

R_GS = 2 x 10⁹ Ohms

R_GS = 2000 x 10⁶ Ohms

Or

R_GS = 2000 Mega Ohms

Example 2: Find the drain current with the following parameters:

I_DSS = 5mA

V_GS = -2 Volts

V_P = -1 volts

Solution:

We know the formula to find the drain current is given by:

I_D = I_DSS (1 - V_GS/V_P)²

Putting the given values in the above equation, we get:

I_D = 5 x 10^-3 (1 - (-2 /-1))²

I_D = 5 x 10^-3 (1 - (2))²

I_D = 5 x 10^-3 (-1)²

I_D = 5 x 10^-3 Amperes

Or

I_D = 5mA

Thus, we can say that I_D = I_DSS = 5mA

Example 3: Find the pinch-off voltage of the n-channel silicon JFET with the following parameters:

N_D = 10¹⁶ cm^-3

A = 0.40um

ε = 8.854 x 10^-14

Solution: We know, the formula to calculate pinch-off voltage is given by:

V_P = qN_Da²/2ε_s

ε_s = ε ε_o

q is the charge of an electron = 1.6 x 10^-19

Putting the given values in the above equation, we get:

V_P =1.6 x 10^-19 x 10¹⁶ x (0.4 x 10^-4)² /2 x 11.7 x 8.854 x 10^-14

V_P = 1.23 Volts