GATE 2017 CS Set 1

49) Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC- relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence

Instr. No.	Instruction
i	add R2, R3, R4
i+1	sub R5, R6, R7
i+2	cmp R1, R9, R10
i+3	beq R1, Offset

If the target of the branch instruction is i, then the decimal value of the Offest is __________.

Answer: A

Explanation:

Here, we assume that the addresses start with 2000 for the first instruction.

Address	Instru. No.	Instruction
2000	i	add R2, R3, R4
2004	i + 1	sub R5, R6, R7
2008	i + 2	cmp R1, R9, R10
2012	i + 3	beq R1, Offset
2016	Next Instruction

According to the question the target of branch instruction is 'i'
So, we need to go to address 2000 from currently pointed address 2016 = 2016?2000 = 16
Now, according to Program Counter(PC) Relative Mode,
Effective PC address = next instruction address + offset = 16 + offset
Hence, Offset = - 16

Therefore option (A) is the correct answer.

50) Instruction execution in a processor is divided into 5 stages. Instruction Fetch(IF), Instruction Decode (ID), Operand Fetch(OF), Execute(EX), and Write Back(WB). These stages take 5, 4, 20, 10 and 3 nanoseconds(ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2ns. Two pipelined implementations of the processor are contemplated:

(i) a na�ve pipeline implementation (NP) with 5 stages and
(ii) an efficient pipeline (EP) where the OF stage id divided into stages OF1 and OF2 with execution times of 12ns and 8ns respectively.

The speedup (correct to two decimals places) achieved by EP over NP in executing 20 independent instructions with no hazards is ________________.

1.50-1.51
1.51-1.52
1.52-1.53
1.53-1.54

Answer: A

Explanation:

Given, total number of instructions = 20

Case 1: For naive pipeline (NP):
Number of stages = 5
Clock cycle time = max { (stage delay + buffer delay) } = { 7, 6, 22, 12, 5 } = 22 ns
Execution time (E_np) = ( Number of stage + number of instructions - 1 ) * Clock cycle time
= ( 5 + 20 - 1)* 22 = 528 ns

Case 2: For efficient pipeline (EP):
number of stages = 6 ( delay with 20 ns stage is divided into 12 ns and 8 ns )
Clock cycle time = max { (stage delay+buffer delay) } = { 7, 6, 14, 10, 14, 5 } = 14 ns
Execution time (E_np) = ( Number of stage + number of instructions - 1 ) * Clock cycle time
= ( 6 + 20 - 1 )* 14 = 350 ns
So, Speedup = (E_np) / (E_np) = 528 / 350 = 1.508

Therefore option (A) is the correct answer.

51) Consider a 2-way set associative cache with 256 blocks and uses LRU replacement, Initially the cache is empty. Conflict misses are those misses which occur due the contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesses to memory blocks:

(0,128,256,128,0,128,256,128,1,129,257,129,1,129,257,129)

is repeated 10 times. The number of conflict misses experienced by the cache is ___________.

Answer: B

Explanation:

1^st Iteration for : { 0,128,256,128,0,128,256,128 }

Block-Id	Type	Set0 Content
0	Compulsory miss	0
128	Compulsory miss	0 128
256	Compulsory miss	128 256
128	Hit	256 128
0	Conflict miss	128 0
128	Hit	0 128
256	Conflict miss	128 256
128	Hit	256 128

So, Total number of conflict misses in set0 = 2
Similarly for: {1,129,257,129,1,129,257,129}
Total number of conflict misses in set1 = 2
Therefore Total number of conflict misses in 1st iteration = 2+2 = 4
2nd iteration for: {0,128,256,128,0,128,256,128}

Block-Id	Type	Set0 Content
0	Conflict miss	128 0
128	Hit	0 128
256	Conflict miss	128 256
128	Hit	256 128
0	Conflict miss	128 0
128	Hit	0 128
256	Conflict miss	128 256
128	Hit	256 128

Total number of conflict misses in set1 = 4.
Similarly for: {1,129,257,129,1,129,257,129}
Total number of conflict misses in set1 = 4
So, Total Number of conflict misses in 2nd iteration = 4 + 4 = 8
Noe the content of each set is same for iterations 3....10. Therefore each of the remaining iterations will also have 8 conflict misses.
Hence, overall conflict misses = 4 + 8 ∗ 9 = 76

Therefore option (B) is the correct answer.

52) Consider the expression (a-1) * ((( b + c ) / 3 )) + d)). Let X be the minimum number of registers required by an optimal code generation (without any register spill) algorithm for a load/store architecture, in which

(i) only load and store instructions can have memory operands and
(ii) arithmetic instructions can have only register or immediate operands.

The value of X is ________.

Answer: A

Explanation:

By using the load/store architecture, the assembly code can be written as follows:
Load R1, b
Load R2, c
ADD R1, R2
Div R1, 3
Load R2, d
Add R1, R2
Load R2, a
Sub R2, 1
Mul R2, R1
Here, only two registers (R1 & R2) are used. Therefore option () is the correct answer.

53) Consider the following C program.

#include <stdio.h>
#include <string.h>
void printlength (char *s, char *t)
{ 
  unsigned int c = 0;
  int len = ((strlen (s) - strlen (t)) > c) ? strlen (s) : strlen (t);
  printf("%dn", len);
}
void main()
{
  char *x = "abc";
  char *y = "defgh";
  printlength(x, y);
}

Recall that strlen is defined in string.h as returning a value of type size_t, which is an unsigned int . The output of the program is _________.

Answer: B

Explanation:

((strlen(s) - strlen(t)) > c) ? strlen (s): strlen (t)
= (3 - 5 > 0)
= (-2 > 0)
From the above, it is clear that the ternary operator "?" will always return strlen(s) which is 3 and assign to len because ternary operator returns first if the condition is true otherwise returned second. So final value will be printed 3.

Therefore option (B) will be the correct answer.

54) A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits.

Answer: B

Explanation:

Direct-Mapped:

Tag field - 10

Line No. (Log N/B)

Offset (Log B)

16-way set-associative:

In this, tag field size = 10 + log216 = 14 bits because for k-way set associative map design, log2k bits are additionally required to the number of bits in tag field for Direct map design.

Tag field - 10

Set No. (Log N/16B)

Offset (Log B)

Therefore, option (B) is the correct answer.

55) The output of executing the following C program is ________.

#include <stdio.h>
int total(int v)
{
 static int count = 0;
 while (v)
  {
   count += v & 1;
  v >>= 1;
  }
return count;
}
void main()
{
  static int x = 0;
  int i = 5;
  for (; i> 0; i--)
{
  x = x + total(i);
  }
printf ("%dn", x) ;
}

Answer: A

Explanation:

According to question, Digits are: 5->0101, 4->0100, 3->0011, 2->0010, 1->0000

So, count of 1s are:

In digit(5) -> Count = 2
In digit(4) -> 2+1 = 3, Count = 3
In digit(3) -> 3+2 = 5, Count = 5
In digit(2) -> 5+1 = 6, Count = 6
In digit(1) -> 6+1 = 7, Count = 7

In the main block it add all the values of outer loop i.e. 2+3+5+6+7 = 23

Therfore, option (A) is the correct answer.

56) After Rajendra Chola returned from his voyage to Indonesia, he ______ to visit the temple in Tanjavur.