Computer Science Quiz - II: Part 2

Topic 5 - Digital Electronics

1) Identify the Idempotent Law and Commutative Law

A * B = B * A and A * A = A
A * A = A and A * B = B * A
~ (~ A) = A and A(B+C) = AB + AC
None of these

Answer: (b) A * A = A and A * B = B * A

Explanation:

Idempotent Law says operating the same operands gives the operand itself as a result. For Example: a + a = a and b . b = b

If A * B = B * A then it is said to be commutative.

2) Which of the following claim is true about Ex-OR Gate?

Ex-OR satisfies Idempotent Law only
Ex-OR satisfies Idempotent Law as well as Commutative Law
Ex-OR satisfies both Commutative and Associative Law but not Idempotent Law
Ex-OR satisfies both Idempotent and Associative law but not Commutative Law

Answer: (c) Ex-OR satisfies both Commutative and Associative Law but not Idempotent Law

Explanation:

Ex-OR does not satisfy Idempotent Law:

a ⊕ a != a instead a ⊕ a = 0

Ex-OR satisfies Commutative Law:

a ⊕ b = b ⊕ a

LHS = a ⊕ b

= a' b + a b'

= b' a + a' b = b ⊕ a

(We know that OR (+) operation is commutative means a + b = b + a).

Hence Proved.

Ex-Or Satisfies Associative Law:

a ⊕ ( b ⊕ c ) = ( a ⊕ b ) ⊕ c

LHS = a ⊕ ( b ⊕ c )

= a ⊕ ( b' c + b c')

= a' ( b' c + b . c') + a ( b' c + b c' )'

= a' b' c + a' b c' + a ( b' c' + b c ) (Complement of Ex-OR is Ex-NOR)

= a' b' c + a' b c' + a b' c' + a b c

RHS = (a ⊕ b) ⊕ c

= ( a' b + a b' ) ⊕ c

= ( a' b + a b' )' c + ( a' b + a b' ) c'

= ( a' b' + a b ) c + a' b c' + a b' c' (Complement of Ex-OR is Ex-NOR)

= a' b' c + a b c + a' b c' + a b' c'

= a' b' c + a' b c' + a b' c' + a b c

= LHS

Hence Proved.

Therefore, (c) is the correct answer.

3) Which of the following claim is true about Ex-NOR Gate?

Ex-NOR satisfies Idempotent Law only
Ex-NOR satisfies Idempotent Law as well as Commutative Law
Ex-NOR satisfies both Commutative and Associative Law but not Idempotent Law
Ex-NOR satisfies both Idempotent and Associative law but not Commutative Law

Answer: (c) Ex-NOR satisfies both Commutative and Associative Law but not Idempotent Law

Explanation:

Ex-NOR does not satisfy Idempotent Law:

a ⊙ a != a instead a ⊙ a = 1

Ex-NOR satisfies Commutative Law:

a ⊙ b = b ⊙ a

LHS = a ⊙ b

= a' b' + a b

= b' a' + b a = b ⊙ a

(We know that AND (.) operation is commutative means a . b = b . a).

Hence Proved.

Ex-Or Satisfies Associative Law:

a ⊙ ( b ⊙ c ) = ( a ⊙ b ) ⊙ c

LHS = a ⊙ ( b ⊙ c )

= a ⊙ ( b' c' + b c)

= a' ( b' c' + b . c)' + a ( b' c' + b c )

= a' ( b'c + b c') + a (b' c' + b c) (Complement of Ex-NOR is Ex-OR)

= a' b' c + a' b c' + a b' c' + a b c

RHS = ( a ⊙ b ) ⊙ c

= ( a' b' + a b ) ⊙ c

= ( a' b' + a b )' c' + ( a' b' + a b ) c

= ( a' b + a b' ) c' + ( a' b' + a b ) c (Complement of Ex-NOR is Ex-OR)

= a' b c' + a b' c' + a' b' c + a b c

= a' b' c + a' b c' + a b' c' + a b c

= LHS

Hence Proved.

Therefore, (c) is the correct answer.

4) How many different Boolean functions can be used with n Boolean variables at most?

2 ^ n²
2 ^ 2ⁿ
2ⁿ
n²

Answer: (b) 2 ^ 2ⁿ

Explanation: With n binary variables, 2ⁿ combinations are possible. Additionally, since there are only two potential values for a Boolean function 0 or 1 the total number of possible functions will be 2^(2ⁿ).

5) How many different degree six Boolean functions exist?

2⁶
2³⁶
2⁶⁴
2¹⁶

Answer: (c) 2⁶⁴

Explanation:

Using formula:

Number of Boolean functions = 2 ^ 2ⁿ

= 2 ^ 2⁶

= 2 ^ 64

Hence, (c) is the correct answer.

6) A Boolean expression's dual is produced by swapping

Boolean Sums and Boolean Products or interchanging 0s and 1s
Boolean Products and Boolean sums and interchanging 1s and 0s
Boolean Products and Boolean Sums
Interchanging 0s and 1s

Answer: (b) A Boolean expression's dual is produced by swapping Boolean Products and Boolean sums and interchanging 1s and 0s

Explanation:

If we take a function f (a, b, c, d, ......, z, 0, 1, +, .) as an example, its dual is defined as fd (a, b, c, ......, z, 0, 1, ., +). Dual functions are referred to when the nature of the variable does not change but 0 ? 1, 1 ? 0, or ? and, and ? or.

When we take the dual of a function, its functionality is preserved, but a positive logic system is changed into a negative logic system because a function is independent of magnitude, if it functions correctly in a positive logic system, it must likewise function correctly in a negative logic system.

7) Select the correct option

The dual of x + y z is

x' + y' z'
x' . ( y' + z' )
x . ( y + z )
x + y z

Answer: (c) x . ( y + z )

Explanation: Dual functions are referred to when the nature of the variable does not change but 0 ? 1, 1 ? 0, or ? and, & and ? or.

8) A Boolean function's dual, denoted by the symbol F^D, is the same expression as the function's original expression with the + and * switched around. If F = F^D, then F is said to be self-dual. With n Boolean variables, there are self-dual functions that total

2n
2n-1
2^2ⁿ
2^2^n-1

Answer: (d) 2^2^n-1

Explanation: There are no terms that are mutually exclusive for a self-dual function. We can therefore choose just one minterm from each pair of mutually exclusive terms

For n variable functions, a total of 2ⁿ minterms are feasible, resulting in 2^n-1 pairs of mutually exclusive minterms. Since there are two options in each pair of mutually exclusive minterms, a total of 2^(2^n-1) self-dual functions are also possible.

9) Using Boolean algebra, the absorption law states that

a + a' . b = a + b
a . a = a
a + a . b = a
None of the above

Answer: (c) a + a . b = a

Explanation:

LHS = a + a . b

= a . ( 1 + b )

= a . 1 = a

Hence Proved.

10) Using Boolean algebra, the compensation theorem states that

a + a' . b = a + b
a . a = a
a + a . b = a
None of the above

Answer: (a) a + a' . b = a + b

Explanation: The above formula can be derived using K-map.

Here, a represents minterm number 2 and 3 and a' b represents minterm number 1.

So, we have obtained two groups of the minterm.

To represent minterm number 2 and 3, we have a and to represent minterm number 1 and 3, we have b.

The minimized equation is a + b = RHS. Hence proved.

11) Take into account the four-variable Boolean function that follows:

F ( w, x, y, z) = ? ( 1, 3, 4, 6, 9, 11, 12, 14)

What is the simplest version of the function that the Karnaugh map may represent?

x' z + x z'
x' z' + x z
w' x + y' z
w y + z y

Answer: (a) x' z + x z'

Explanation:

Using K-map, we have

Image Here:

There are two groups of minterms:

? ( 4, 6, 12, 14) can be represented by x z',

? ( 1, 3, 9, 11) can be represented by x' z.

The minimized function is x z' + x' z.

Therefore, (a) is the correct answer.

12) Which is an example of universal gate?

Ex-OR gate
Ex-NOR gate
ANS gate
NOR gate

Answer: (d) NOR gate

Explanation: NAND and NOR gates are the universal gates. We can implement any Boolean function using any of these universal gates.

13) Logic gates can be used to implement an equation for the sum of products.

AND - OR
NAND - OR
AND - NOT
OR - AND

Answer: (a) AND - OR

Explanation:

It is a two-level implementation. In the first level, we use AND gates to find the product terms of the Boolean equation and in the second level, we use OR gate to sum those product terms. Eventually, we get the equation in the form of SOP (sum of products.)

Image Here

14) How many NAND gates must be used as a minimum to build a 2-input EXCLUSIVE-OR function without the aid of any other logic gates?

Answer: (c) 4

Explanation: Circuit is shown in the figure below:

Image Here

15) Select the correct option

Half adder is Ex-OR and AND Circuit
Half adder is Ex-NOR and AND Circuit
Half adder is NAND and NOR Circuit
Half Adder is AND and OR Circuit

Answer: (a) Half adder is Ex-OR and AND Circuit

Explanation:

Half-adders are combinational circuits that execute the arithmetic addition of two one-bit binary values. Therefore, two single binary bits A and B are added in half adders, and two outputs, sum (S) and carry (c), are produced.

It is implemented using Ex-OR and AND gates. Ex-OR determines the SUM and AND determines the Carry as shown below:

Image Here

16) Which of the subsequent statements is accurate?

I. A half adder is a circuit that adds two bits to produce a sum bit and a carry bit.

II. A full adder is a circuit that adds two bits to produce a sum bit and a carry bit.

III. A circuit known as a full adder produces a sum bit and a carry bit by adding two bits and a carry bit.

IV. An inverter is a piece of equipment that takes the value of a Boolean variable as input and outputs its complement.

I, II, and IV only
III and IV only
I and II only
I, III, and IV only

Answer: (d) I, III, IV only

Explanation:

Half Adders - Half-adders are combinational circuits that execute the arithmetic addition of two one-bit binary values. Therefore, two single binary bits A and B are added in half adders, and two outputs, sum (S) and carry (c), are produced.

Full Adders - The arithmetic addition of three input bits is carried out by a complete adder, a combinational logic circuit.

SUM = A_n + B_n + C_n-1

Where C_n-1is the carry created by adding the (n-1)^th order bits, and A_n, B_n are the nth order bits of the numbers A and B, respectively.

Inverter - An inverter, often known as a NOT gate, is a logic gate used in digital logic to implement logical negation. When a bit is input, it outputs the exact opposite bit. Usually, the bits are implemented as two contrasting voltage levels.

Therefore, option I, III, and IV are true and II is false. Hence, (d) is the correct answer.

17) Consider the following input values for a full - adder:

I. x = 0, y = 1 and C_i (Carry Input) = 1

II. x = 1, y = 0 and C_i = 0

For the aforementioned input numbers, calculate the values of S (sum) and C_o (carry output).

S = 1, C_o = 0 and S = 0, C_o = 1
S = 0, C_o = 1 and S = 1, C_o = 0
S = 0, C_o = 0 and S = 1, C_o = 1
S = 1, C_o = 0 and S = 1, C_o = 0

Answer: (b) S = 0, C_o = 1 and S = 1, C_o = 0

Explanation:

For a full adder:

Sum = A ⊕ B ⊕ C, and

Carry = A . B + B . C + A . C

I. x = 0, y = 1 and C_i = 1

Sum = 0 ⊕ 1 ⊕ 1 = 0

Carry =0 . 1 + 1 . 1 + 0 . 1 = 0 + 1 + 0 = 1

II. x = 1, y = 0, and Ci = 0

Sum = 1 ⊕ 0 ⊕ 0 = 1

Carry = 1 . 0 + 0 . 0 + 1 . 0 = 0 + 0 + 0 = 0

Hence, (b) is the correct answer.

18) A logic circuit that __________ is a multiplexer.

requires one input to produce several outputs
has several inputs and outputs
accepts numerous inputs and produces just one output
requires one input and produces one output

Answer: (c) A logic circuit that accepts numerous inputs and produces just one output is a multiplexer.

Explanation:

A unique and popular type of combinational circuit is the multiplexer. The primary criterion is that we must choose one input from a large number of inputs, such as a telephone call or a train departing the station.

Using a combinational circuit known as a multiplexer, binary data is chosen from one or more input lines and sent to a single output line. A group of selection lines regulates the choice of a specific input line.

There are n selection lines and 2n input lines, and the bit combinations on the selection lines determine which input is chosen. Since it chooses one of the numerous inputs and directs the binary data to the output line, a multiplexer is also known as a data selector.

Image Here

Hence, (c) is the correct answer.

19) If both the S and R inputs of an SR latch created by cross-coupling two NAND gates are set to 0, the following will be the result:

Q = 0 and Q' = 1
Q = 1 and Q' = 0
Q = 1 and Q' = 1
Indeterminate state

Answer: (c) and (d) both options are correct

Explanation:

Image Here

Truth Table

S	R	Q_n	Q_{n + 1}
0	0	0	X (Don't Care)
0	0	1	X (Don't Care)
0	1	0	1
0	1	1	1
1	0	0	0
1	0	1	0
1	1	0	0
1	1	1	1

We shall obtain both Q and Q' as 1 when R and S are set to 0. This output will last forever and does not depend on the inputs and not on the sequence in which events occur. The output leads to an uncertain state.

However, if R = S = 1 is set after this state, the circuit will act like a buffer, and Q will remain Q. (Either Q = 0, and Q' = 1 or Q = 1 and Q' = 0).

Thus, the correct answer is both (c) and (d).

20) Think of a 4-bit Johnson counter with the value 0000 as its starting point. This counter's counting pattern is

0, 1, 3, 7, 15, 14, 12, 8, 0
0, 1, 3, 5, 7, 9, 11, 13, 15, 0
0, 2, 4, 6, 8, 10, 12, 14, 0
0, 8, 12, 14, 15, 7, 3, 1, 0

Answer: (d) 0, 8, 12, 14, 15, 7, 3, 1, 0

Explanation: The complement of the last shift register's output is connected to the first shift register's input by the four-bit Johnson's counter, with the shift distance set to 1, meaning that one bit will cycle.

This is how it will operate:

0000 = 0 (Complementing the last 0 and feeding it into the first register)

1000 = 8

1100 = 12

1110 = 14

1111 = 15 (Complementing the last 1 and feeding it into the first register)

0111 = 7

0011 = 3

0001 = 1

0000 = 0

Therefore (d) is the correct answer.

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