D flip-flop is a slight modification of clocked SR flip-flop.
From the above figure, you can see that the D input is connected to the S input and the complement of the D input is connected to the R input.
When the value of CP is '1' (HIGH), the flip-flop moves to the SET state if it is '0' (LOW), the flip-flop switches to the CLEAR state.
Next TopicJK Flip-Flop
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