Verilog Control Blocks
Hardware behavior cannot be implemented without conditional statements and other ways to control the flow of logic. Verilog has a set of mechanisms and control flow blocks.
This conditional statement is used to decide whether certain statements will be executed or not. It is very similar to the if-else-if statements in C language. If the expression evaluates to true, then the first statement will be executed.
If the expression evaluates to false and if an else part exists, the else part will be executed.
Following is the most simplified syntax of the if-else-if conditional statement:
The else part of an if-else is optional, and it can create confusion. To avoid this confusion, it's easier to always associate the else to the previous if that lacks an else. Another way is to enclose statements within a begin-end block. The last else part handles the none-of-the-above or default case where none of the other conditions were satisfied.
Loops provide a way of executing single or multiple statements within a block one or more number of times. In Verilog, there are four different types of looping statements.
1. Forever loop
This loop will continuously execute the statements within the block.
After the execution of the above example, it produces the following data.
2. Repeat loop
This will execute statements a fixed number of times. If the expression evaluates to an X or Z, it will be treated as zero and not executed.
The above code generates the following outcome.
3. ile loop
This will execute statements as long as an expression is true and will exit once the condition becomes false. If the condition is false from the start, statements will not be executed at all.
Run the above code, and we will get the following output.
4. For loop
For loop controls the statements using a three-step process:
After execution the for loop code, the output looks like