Verilog Data Types
Verilog introduces several new data types. These data types make RTL descriptions easier to write and understand.
The data storage and transmission elements found in digital hardware are represented using a set of Verilog Hardware Description Language (HDL) data types.
In Verilog, data types are divided into NETS and Registers. These data types differ in the way that they are assigned and hold values, and also they represent different hardware structures.
The Verilog HDL value set consists of four basic values:
Integer and Real Data Types
Many data types will be familiar to C programmers. The idea is that algorithms modeled in C can be converted to Verilog if the two languages have the same data types.
Verilog introduces new two-state data types, where each bit is 0 or 1 only. Using two-state variables in RTL models may enable simulators to be more efficient. And they are not affecting the synthesis results.
Unlike in C, Verilog specifies the number of bits for the fixed-width types.
We preferred logic because it is better than reg. We can use logic where we have used reg or wire.
Non-Integer Data Types
In Verilog, we can define scalar and vector nets and variables. We can also define memory arrays, which are one-dimensional arrays of a variable type.
Verilog allowed multi-dimensioned arrays of both nets and variables and removed some of the restrictions on memory array usage.
Verilog takes this a stage further and refines the concept of arrays and permits more operations on arrays.
In Verilog, arrays may have either packed or unpacked dimensions, or both.
It can be arranged in memory in any way that the simulator chooses. We can reliably copy an array on to another array of the same type.
For arrays with different types, we have to use a cast, and there are rules for how an unpacked type is cast to a packed type.
Verilog permits several operations on complete unpacked arrays and slices of unpacked arrays.
For these, the arrays or slices involved must have the same type and shape, i.e., the same number and lengths of unpacked dimensions.
The packed dimensions may differ, as long as the array or slice elements have the same number of bits. The permitted operations are:
Verilog also includes dynamic arrays (the number of elements may change during simulation) and associative arrays (which have a non-contiguous range).
Verilog includes several arrays of querying functions and methods to support all these array types.
Nets are used to connect between hardware entities like logic gates and hence do not store any value.
The net variables represent the physical connection between structural entities such as logic gates. These variables do not store values except trireg. These variables have the value of their drivers, which changes continuously by the driving circuit.
Some net data types are wire, tri, wor, trior, wand, triand, tri0, tri1, supply0, supply1, and trireg. A net data type must be used when a signal is:
A wire does not store its value but must be driven by a continuous assignment statement or by connecting it to the output of a gate or module.
2. Wand (wired-AND)
3. Wor (wired-OR)
4. Tri (three-state)
5. Supply0 and Supply1
A register is a data object that stores its value from one procedural assignment to the next. They are used only in functions and procedural blocks.
An assignment statement in a procedure acts as a trigger that changes the value of the data storage element.
Reg is a Verilog variable type and does not necessarily imply a physical register. In multi-bit registers, data is stored as unsigned numbers, and no sign extension is done for what the user might have thought were two's complement numbers.
Some register data types are reg, integer, time, and real.reg is the most frequently used type.
Note: A reg need not always represent a flip-flop because it can also represent combinational logic.
Strings are stored in reg, and the width of the reg variable has to be large enough to hold the string.
Each character in a string represents an ASCII value and requires 1 byte. If the variable's size is smaller than the string, then Verilog truncates the leftmost bits of the string. If the variable's size is larger than the string, then Verilog adds zeros to the left of the string.