Computer Science Quiz  II: Part 2Topic 5  Digital Electronics1) Identify the Idempotent Law and Commutative Law
Answer: (b) A * A = A and A * B = B * A Explanation: Idempotent Law says operating the same operands gives the operand itself as a result. For Example: a + a = a and b . b = b If A * B = B * A then it is said to be commutative. 2) Which of the following claim is true about ExOR Gate?
Answer: (c) ExOR satisfies both Commutative and Associative Law but not Idempotent Law Explanation: ExOR does not satisfy Idempotent Law: a ⊕ a != a instead a ⊕ a = 0 ExOR satisfies Commutative Law: a ⊕ b = b ⊕ a LHS = a ⊕ b = a' b + a b' = b' a + a' b = b ⊕ a (We know that OR (+) operation is commutative means a + b = b + a). Hence Proved. ExOr Satisfies Associative Law: a ⊕ ( b ⊕ c ) = ( a ⊕ b ) ⊕ c LHS = a ⊕ ( b ⊕ c ) = a ⊕ ( b' c + b c') = a' ( b' c + b . c') + a ( b' c + b c' )' = a' b' c + a' b c' + a ( b' c' + b c ) (Complement of ExOR is ExNOR) = a' b' c + a' b c' + a b' c' + a b c RHS = (a ⊕ b) ⊕ c = ( a' b + a b' ) ⊕ c = ( a' b + a b' )' c + ( a' b + a b' ) c' = ( a' b' + a b ) c + a' b c' + a b' c' (Complement of ExOR is ExNOR) = a' b' c + a b c + a' b c' + a b' c' = a' b' c + a' b c' + a b' c' + a b c = LHS Hence Proved. Therefore, (c) is the correct answer. 3) Which of the following claim is true about ExNOR Gate?
Answer: (c) ExNOR satisfies both Commutative and Associative Law but not Idempotent Law Explanation: ExNOR does not satisfy Idempotent Law: a ⊙ a != a instead a ⊙ a = 1 ExNOR satisfies Commutative Law: a ⊙ b = b ⊙ a LHS = a ⊙ b = a' b' + a b = b' a' + b a = b ⊙ a (We know that AND (.) operation is commutative means a . b = b . a). Hence Proved. ExOr Satisfies Associative Law: a ⊙ ( b ⊙ c ) = ( a ⊙ b ) ⊙ c LHS = a ⊙ ( b ⊙ c ) = a ⊙ ( b' c' + b c) = a' ( b' c' + b . c)' + a ( b' c' + b c ) = a' ( b'c + b c') + a (b' c' + b c) (Complement of ExNOR is ExOR) = a' b' c + a' b c' + a b' c' + a b c RHS = ( a ⊙ b ) ⊙ c = ( a' b' + a b ) ⊙ c = ( a' b' + a b )' c' + ( a' b' + a b ) c = ( a' b + a b' ) c' + ( a' b' + a b ) c (Complement of ExNOR is ExOR) = a' b c' + a b' c' + a' b' c + a b c = a' b' c + a' b c' + a b' c' + a b c = LHS Hence Proved. Therefore, (c) is the correct answer. 4) How many different Boolean functions can be used with n Boolean variables at most?
Answer: (b) 2 ^ 2^{n} Explanation: With n binary variables, 2^{n} combinations are possible. Additionally, since there are only two potential values for a Boolean function 0 or 1 the total number of possible functions will be 2^(2^{n}). 5) How many different degree six Boolean functions exist?
Answer: (c) 2^{64} Explanation: Using formula: Number of Boolean functions = 2 ^ 2^{n} = 2 ^ 2^{6} = 2 ^ 64 Hence, (c) is the correct answer. 6) A Boolean expression's dual is produced by swapping
Answer: (b) A Boolean expression's dual is produced by swapping Boolean Products and Boolean sums and interchanging 1s and 0s Explanation: If we take a function f (a, b, c, d, ......, z, 0, 1, +, .) as an example, its dual is defined as fd (a, b, c, ......, z, 0, 1, ., +). Dual functions are referred to when the nature of the variable does not change but 0 ? 1, 1 ? 0, or ? and, and ? or. When we take the dual of a function, its functionality is preserved, but a positive logic system is changed into a negative logic system because a function is independent of magnitude, if it functions correctly in a positive logic system, it must likewise function correctly in a negative logic system. 7) Select the correct option The dual of x + y z is
Answer: (c) x . ( y + z ) Explanation: Dual functions are referred to when the nature of the variable does not change but 0 ? 1, 1 ? 0, or ? and, & and ? or. 8) A Boolean function's dual, denoted by the symbol F^{D}, is the same expression as the function's original expression with the + and * switched around. If F = F^{D}, then F is said to be selfdual. With n Boolean variables, there are selfdual functions that total
Answer: (d) 2^2^{n1} Explanation: There are no terms that are mutually exclusive for a selfdual function. We can therefore choose just one minterm from each pair of mutually exclusive terms For n variable functions, a total of 2^{n} minterms are feasible, resulting in 2^{n1} pairs of mutually exclusive minterms. Since there are two options in each pair of mutually exclusive minterms, a total of 2^(2^{n1}) selfdual functions are also possible. 9) Using Boolean algebra, the absorption law states that
Answer: (c) a + a . b = a Explanation: LHS = a + a . b = a . ( 1 + b ) = a . 1 = a Hence Proved. 10) Using Boolean algebra, the compensation theorem states that
Answer: (a) a + a' . b = a + b Explanation: The above formula can be derived using Kmap. Here, a represents minterm number 2 and 3 and a' b represents minterm number 1. So, we have obtained two groups of the minterm. To represent minterm number 2 and 3, we have a and to represent minterm number 1 and 3, we have b. The minimized equation is a + b = RHS. Hence proved. 11) Take into account the fourvariable Boolean function that follows: F ( w, x, y, z) = ? ( 1, 3, 4, 6, 9, 11, 12, 14) What is the simplest version of the function that the Karnaugh map may represent?
Answer: (a) x' z + x z' Explanation: Using Kmap, we have Image Here: There are two groups of minterms: ? ( 4, 6, 12, 14) can be represented by x z', ? ( 1, 3, 9, 11) can be represented by x' z. The minimized function is x z' + x' z. Therefore, (a) is the correct answer. 12) Which is an example of universal gate?
Answer: (d) NOR gate Explanation: NAND and NOR gates are the universal gates. We can implement any Boolean function using any of these universal gates. 13) Logic gates can be used to implement an equation for the sum of products.
Answer: (a) AND  OR Explanation: It is a twolevel implementation. In the first level, we use AND gates to find the product terms of the Boolean equation and in the second level, we use OR gate to sum those product terms. Eventually, we get the equation in the form of SOP (sum of products.) Image Here 14) How many NAND gates must be used as a minimum to build a 2input EXCLUSIVEOR function without the aid of any other logic gates?
Answer: (c) 4 Explanation: Circuit is shown in the figure below: Image Here 15) Select the correct option
Answer: (a) Half adder is ExOR and AND Circuit Explanation: Halfadders are combinational circuits that execute the arithmetic addition of two onebit binary values. Therefore, two single binary bits A and B are added in half adders, and two outputs, sum (S) and carry (c), are produced. It is implemented using ExOR and AND gates. ExOR determines the SUM and AND determines the Carry as shown below: Image Here 16) Which of the subsequent statements is accurate? I. A half adder is a circuit that adds two bits to produce a sum bit and a carry bit. II. A full adder is a circuit that adds two bits to produce a sum bit and a carry bit. III. A circuit known as a full adder produces a sum bit and a carry bit by adding two bits and a carry bit. IV. An inverter is a piece of equipment that takes the value of a Boolean variable as input and outputs its complement.
Answer: (d) I, III, IV only Explanation: Half Adders  Halfadders are combinational circuits that execute the arithmetic addition of two onebit binary values. Therefore, two single binary bits A and B are added in half adders, and two outputs, sum (S) and carry (c), are produced. Full Adders  The arithmetic addition of three input bits is carried out by a complete adder, a combinational logic circuit. SUM = A_{n} + B_{n} + C_{n1} Where C_{n1}is the carry created by adding the (n1)^{th} order bits, and A_{n}, B_{n} are the nth order bits of the numbers A and B, respectively. Inverter  An inverter, often known as a NOT gate, is a logic gate used in digital logic to implement logical negation. When a bit is input, it outputs the exact opposite bit. Usually, the bits are implemented as two contrasting voltage levels. Therefore, option I, III, and IV are true and II is false. Hence, (d) is the correct answer. 17) Consider the following input values for a full  adder: I. x = 0, y = 1 and C_{i} (Carry Input) = 1 II. x = 1, y = 0 and C_{i} = 0 For the aforementioned input numbers, calculate the values of S (sum) and C_{o} (carry output).
Answer: (b) S = 0, C_{o} = 1 and S = 1, C_{o} = 0 Explanation: For a full adder: Sum = A ⊕ B ⊕ C, and Carry = A . B + B . C + A . C I. x = 0, y = 1 and C_{i} = 1 Sum = 0 ⊕ 1 ⊕ 1 = 0 Carry =0 . 1 + 1 . 1 + 0 . 1 = 0 + 1 + 0 = 1 II. x = 1, y = 0, and Ci = 0 Sum = 1 ⊕ 0 ⊕ 0 = 1 Carry = 1 . 0 + 0 . 0 + 1 . 0 = 0 + 0 + 0 = 0 Hence, (b) is the correct answer. 18) A logic circuit that __________ is a multiplexer.
Answer: (c) A logic circuit that accepts numerous inputs and produces just one output is a multiplexer. Explanation: A unique and popular type of combinational circuit is the multiplexer. The primary criterion is that we must choose one input from a large number of inputs, such as a telephone call or a train departing the station. Using a combinational circuit known as a multiplexer, binary data is chosen from one or more input lines and sent to a single output line. A group of selection lines regulates the choice of a specific input line. There are n selection lines and 2n input lines, and the bit combinations on the selection lines determine which input is chosen. Since it chooses one of the numerous inputs and directs the binary data to the output line, a multiplexer is also known as a data selector. Image Here Hence, (c) is the correct answer. 19) If both the S and R inputs of an SR latch created by crosscoupling two NAND gates are set to 0, the following will be the result:
Answer: (c) and (d) both options are correct Explanation: Image Here Truth Table
We shall obtain both Q and Q' as 1 when R and S are set to 0. This output will last forever and does not depend on the inputs and not on the sequence in which events occur. The output leads to an uncertain state. However, if R = S = 1 is set after this state, the circuit will act like a buffer, and Q will remain Q. (Either Q = 0, and Q' = 1 or Q = 1 and Q' = 0). Thus, the correct answer is both (c) and (d). 20) Think of a 4bit Johnson counter with the value 0000 as its starting point. This counter's counting pattern is
Answer: (d) 0, 8, 12, 14, 15, 7, 3, 1, 0 Explanation: The complement of the last shift register's output is connected to the first shift register's input by the fourbit Johnson's counter, with the shift distance set to 1, meaning that one bit will cycle. This is how it will operate: 0000 = 0 (Complementing the last 0 and feeding it into the first register) 1000 = 8 1100 = 12 1110 = 14 1111 = 15 (Complementing the last 1 and feeding it into the first register) 0111 = 7 0011 = 3 0001 = 1 0000 = 0 Therefore (d) is the correct answer.
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